IBM PowerPC 603

Historia

The PowerPC 600 family was the first family of PowerPC processors built. The first incarnation became the PowerPC 601 in 1993, and the second generation soon followed with the PowerPC 603, PowerPC 604 and the 64-bit PowerPC 620 The PowerPC 603 was the first processor implementing the complete 32-bit PowerPC Architecture as specified. It was designed to be a low cost, low end processor for portable and embedded use. One of the main features was power saving functions (doze, nap and sleep mode) that could dramatically reduce power requirements, drawing only 2 mW in sleep mode. The 603 has a four-stage pipeline and five execution units: integer unit, floating point unit, branch prediction unit, load/store unit and a system registry unit. It has separate 8 KB L1 caches for instructions and data and a 32/64 bit 60x memory bus, reaching up to 75 MHz. The 603 core did not have hardware support for SMP. A 200 MHz Motorola PowerPC 603 in a ceramic Ball Grid Array packaging. The PowerPC 603 had 1.6 million transistors and was fabricated by IBM and Motorola in a 0.5 μm CMOS process with four levels of interconnect. The die was 85 mm2 large drawing 3 W at 80 MHz. The 603 architecture is the direct ancestor to the PowerPC 750 architecture, marketed by Apple as the PowerPC G3. The 603 was intended to be used for portable Apple Macintosh computers but could not run 68K emulation software with performance Apple considered adequate, due to the smaller processor caches. As a result, Apple chose to only use the 603 in its low-cost desktop Performa line